

   ---- Transcoding 'D:\Projects\Altium\TI\XWRL6432_EVM\PCB_CAD\AWRL6432_IN_CABIN_REF_DES\Rev_A\Board File\Project Outputs for AWRL6432_REF_DESIGN\AWRL6432_REF_DESIGN_274XGBR_REVA\AWRL6432_REF_DESIGN_PCB.GD1' ----   Wed Aug 14 19:38:47 2024

D10   --> D103
D13   --> D104
D15   --> D105
D18   --> D106
D19   --> D107
-----------------------------------------------------------------


   ---- Transcoding 'D:\Projects\Altium\TI\XWRL6432_EVM\PCB_CAD\AWRL6432_IN_CABIN_REF_DES\Rev_A\Board File\Project Outputs for AWRL6432_REF_DESIGN\AWRL6432_REF_DESIGN_274XGBR_REVA\AWRL6432_REF_DESIGN_PCB.GG1' ----   Wed Aug 14 19:38:47 2024

D13   --> D108
D15   --> D109
-----------------------------------------------------------------


   ---- Transcoding 'D:\Projects\Altium\TI\XWRL6432_EVM\PCB_CAD\AWRL6432_IN_CABIN_REF_DES\Rev_A\Board File\Project Outputs for AWRL6432_REF_DESIGN\AWRL6432_REF_DESIGN_274XGBR_REVA\AWRL6432_REF_DESIGN_PCB.GM2' ----   Wed Aug 14 19:38:47 2024

D10   --> D110
D11   --> D111
D13   --> D112
-----------------------------------------------------------------


   ---- Transcoding 'D:\Projects\Altium\TI\XWRL6432_EVM\PCB_CAD\AWRL6432_IN_CABIN_REF_DES\Rev_A\Board File\Project Outputs for AWRL6432_REF_DESIGN\AWRL6432_REF_DESIGN_274XGBR_REVA\AWRL6432_REF_DESIGN_PCB.GM9' ----   Wed Aug 14 19:38:47 2024

D10   --> D113
D13   --> D114
D14   --> D115
-----------------------------------------------------------------


   ---- Transcoding 'D:\Projects\Altium\TI\XWRL6432_EVM\PCB_CAD\AWRL6432_IN_CABIN_REF_DES\Rev_A\Board File\Project Outputs for AWRL6432_REF_DESIGN\AWRL6432_REF_DESIGN_274XGBR_REVA\AWRL6432_REF_DESIGN_PCB.GM10' ----   Wed Aug 14 19:38:47 2024

D10   --> D116
D11   --> D117
D13   --> D118
D14   --> D119
D15   --> D120
D16   --> D121
-----------------------------------------------------------------


   ---- Transcoding 'D:\Projects\Altium\TI\XWRL6432_EVM\PCB_CAD\AWRL6432_IN_CABIN_REF_DES\Rev_A\Board File\Project Outputs for AWRL6432_REF_DESIGN\AWRL6432_REF_DESIGN_274XGBR_REVA\AWRL6432_REF_DESIGN_PCB.GM11' ----   Wed Aug 14 19:38:47 2024

D10   --> D122
D13   --> D123
D15   --> D124
-----------------------------------------------------------------


   ---- Transcoding 'D:\Projects\Altium\TI\XWRL6432_EVM\PCB_CAD\AWRL6432_IN_CABIN_REF_DES\Rev_A\Board File\Project Outputs for AWRL6432_REF_DESIGN\AWRL6432_REF_DESIGN_274XGBR_REVA\AWRL6432_REF_DESIGN_PCB.GM12' ----   Wed Aug 14 19:38:47 2024

D10   --> D125
D11   --> D126
D13   --> D127
D15   --> D128
D18   --> D129
-----------------------------------------------------------------


   ---- Transcoding 'D:\Projects\Altium\TI\XWRL6432_EVM\PCB_CAD\AWRL6432_IN_CABIN_REF_DES\Rev_A\Board File\Project Outputs for AWRL6432_REF_DESIGN\AWRL6432_REF_DESIGN_274XGBR_REVA\AWRL6432_REF_DESIGN_PCB.GTO' ----   Wed Aug 14 19:38:47 2024

D12   --> D130
-----------------------------------------------------------------


   ---- Transcoding 'D:\Projects\Altium\TI\XWRL6432_EVM\PCB_CAD\AWRL6432_IN_CABIN_REF_DES\Rev_A\Board File\Project Outputs for AWRL6432_REF_DESIGN\AWRL6432_REF_DESIGN_274XGBR_REVA\AWRL6432_REF_DESIGN_PCB.GD2' ----   Wed Aug 14 19:38:47 2024

D10   --> D131
D13   --> D132
D15   --> D133
D18   --> D134
D19   --> D135
-----------------------------------------------------------------


   ---- Transcoding 'D:\Projects\Altium\TI\XWRL6432_EVM\PCB_CAD\AWRL6432_IN_CABIN_REF_DES\Rev_A\Board File\Project Outputs for AWRL6432_REF_DESIGN\AWRL6432_REF_DESIGN_274XGBR_REVA\AWRL6432_REF_DESIGN_PCB.GG2' ----   Wed Aug 14 19:38:47 2024

D13   --> D136
D15   --> D137
-----------------------------------------------------------------


   ---- Transcoding 'D:\Projects\Altium\TI\XWRL6432_EVM\PCB_CAD\AWRL6432_IN_CABIN_REF_DES\Rev_A\Board File\Project Outputs for AWRL6432_REF_DESIGN\AWRL6432_REF_DESIGN_274XGBR_REVA\AWRL6432_REF_DESIGN_PCB.GM' ----   Wed Aug 14 19:38:47 2024

D103  --> D138
-----------------------------------------------------------------
